ASIC and FPGA Verification: A Guide to Component Modeling (Systems on Silicon)

by Richard Munden
"As large and complex as today's FPGAs are, they always end up on a board..." ( more)

Key Phrases: path delay section, negative timing constraints, skew violation, Free Model Foundry, Output Glitch Detection Variables, Vital Memo (more...)

Review
Today it is still very difficult to verify board or larger system designs through simulation or any other technique. This important book addresses the largest ingredient needed to make simulation possible the availability of integrated circuit component models. Addressed inside is how to use VITAL extensions and other conventions with VHDL to develop inter operable, reusable models. Only by adopting the standards and practices described in this book can the industry benefit and make system simulation feasible.

Randy Harr, Sevni Technology

This book provides not only an excellent reference for those who write component models for board level verification, but also a much needed introduction to SDF and VITAL for timing simulation.

Hardy Pottinger, University of Missouri-Rolla

Book Description
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs.

ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

• Provides numerous models and a clearly defined methodology for performing board-level simulation.
• Covers the details of modeling for verification of both logic and timing.
• First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.